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general description the ds4830 provides a complete optical control, calibra- tion, and monitor solution based on a low-power, 16-bit, microcontroller core, providing program and ram data memory. i/o resources include a fast/accurate analog-to- digital converter (adc), fast comparators with an internal comparison digital-to-analog converter (dac), 12-bit dacs, 12-bit pwms, internal and external temperature sensors, fast sample/hold, i 2 c slave host interface, and a multiprotocol serial master/slave interface. direct connection of diode-connected transistors, used as remote temperature sensors, is supported as well as expansion to additional external digital temperature sen- sor ics using the on-chip master i 2 c interface. an inde- pendent slave i 2 c interface facilitates communication to a host microprocessor in addition to password-protected in-system reprogramming of the on-chip flash. firmware development is supported by third-party highly versatile c-compilers and development software that programs flash and performs in-circuit debug through the integrated jtag interface and associated hardware. applications pon diplexers and triplexers: gpon, 10gepon, xpon olt, onu optical transceivers: xfp, sfp, sfp+, qsfp, 40g, 100g features s 16-bit low-power microcontroller s 36 kwords total program memory ? 32 kwords flash program memory ? 4 kwords rom program memory s 1 kwords data ram s 8 dac channels ? 12-bit buffered voltage dacs ? internal or external reference s 10 pwm channels ? boost/buck dc-dc control with support for 7-bit to 12-bit resolution and 1mhz switching frequency ? supports 4-channel tecc h-bridge control s 8-bit fast comparator with 16-input mux ? 1.6s per comparison s 13-bit a/d converter with 26-input mux (27ksps) s temperature measurement analog front-end ? internal temperature sensor, 3nc ? 0.0625nc resolution ? supports two external temperature sensors ? differential rail-rail inputs s 31 gpio pins s maskable interrupt sources s internal 20mhz oscillator, cpu core frequency 10mhz ? 4% accurate from 0nc to +50nc s up to 133mhz external clock for pwm and timers s slave communication interface: spi or 400khz i 2 c-compatible 2-wire s master communication interface: spi, 400khz i 2 c- compatible, or maxim 3-wire laser driver s i 2 c and jtag bootloader s two 16-bit timers s 2.97v to 3.63v operating voltage range s brownout monitor s jtag port with in-system debug and programming s low power consumption (16ma) with all analog active typical application circuit appears at end of data sheet. 19-5934; rev 2; 6/13 ordering information appears at end of data sheet. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maximintegrated.com/errata. for related parts and recommended products to use with this part, refer to: www.maximintegrated.com/ds4830.related ds4830 optical microcontroller for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.
2 v dd to gnd ........................................................ -0.3v to +3.97v scl, sda, rst ................................................... -0.3v to +3.63v all other pins to gnd except reg18 and reg285 ............... -0.3v to (v dd + 0.5v)* continuous sink current .................... 20ma per pin, 50ma total continuous source current ................ 20ma per pin, 50ma total operating temperature range .......................... -40nc to +85nc storage temperature range ............................ -55nc to +125nc lead temperature (soldering, 10s) ............................ +300nc soldering temperature (reflow) .................................. +260nc absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions (t a = -40nc to +85nc, unless otherwise noted.) dc electrical characteristics (v dd = 2.97v to 3.63v, t a = -40nc to +85nc, unless otherwise noted. typical values are at v dd = 3.3v, t a = +25nc.) *subject to not exceeding +3.97v. parameter symbol conditions min typ max units v dd operating voltage v dd (note 1) 2.97 3.63 v input logic-high v ih 0.7 x v dd v dd + 0.3 v input logic-low v il -0.3 0.3 x v dd v parameter symbol conditions min typ max units supply current i cpu cpu mode, all analog disabled (notes 2, 3) 4.8 ma i fastcomp 2 i sampleholds both sample/hold 1.5 i adc 2.8 i dacs per channel (note 4) 0.6 brownout voltage v bo monitors v dd (note 1) 2.7 v brownout hysteresis v boh monitors v dd (note 1) 0.07 v 1.8v regulator initial voltage v reg18 (note 1) 1.71 1.8 1.89 v 2.85v regulator initial voltage v reg285 (note 1) 2.8 2.85 2.9 v ds4830 optical microcontroller maxim integrated
3 dc electrical characteristics (continued) (v dd = 2.97v to 3.63v, t a = -40nc to +85nc, unless otherwise noted. typical values are at v dd = 3.3v, t a = +25nc.) parameter symbol conditions min typ max units clock frequencies f osc- peripheral t a = +25nc (note 5) 20 mhz f mosc-core t a = +25nc (note 5) 10 clock error f err t a = -40nc to +85nc 8 % external clock input f xclk 20 133 mhz voltage range: gp[15:0], shen, dacpw[7:0], refina, refinb v range (note 1) -0.3 v dd + 0.3 v output logic-low: scl, sda, mdio, mdi, mcl, mcs, refina, refinb, all gpio pins v ol1 i ol = 4ma (note 1) 0.4 v output logic-high: sda, mdio, mdi, mcl, mcs, refina, refinb, all gpio pins not open drain v oh1 i oh = -4ma (note 1) v dd - 0.5 v pullup current: mdio, mdi, mcl, mcs, all gpio pins i pu1 v pin = 0v 26 55 78 fa gpio drive strength, extra strong outputs: gp0, gp1, mcs, pw8, pw9 r hist 9 27.6 w r lost 8 25.2 gpio drive strength, strong outputs: mdi, dacpw3, dacpw6 r hia 17 32.4 w r loa 12 26.4 gpio drive strength, excluding strong gpio outputs r hib 27 57 w r lob 31 63 ds4830 optical microcontroller maxim integrated
4 dac dc electrical characteristics (v dd = 2.97v to 3.63v, t a = -40nc to +85nc, unless otherwise noted. typical values are at v dd = 3.3v, t a = +25nc.) fast comparator/quick trips dc electrical characteristics (v dd = 2.97v to 3.63v, t a = -40nc to +85nc, unless otherwise noted. typical values are at v dd = 3.3v, t a = +25nc.) parameter symbol conditions min typ max units dac resolution dac r 12 bits dac internal reference accuracy dacrefacc 2.5v internal reference -1.25 +1.25 % dac internal reference power-up speed t dacpup 99% settled 10 fs reference input full-scale range (refina, refinb) reffs 1 2.5 v dac operating current i dacs per channel see the dc electrical characteristics dac integral nonlinearity dacinl 12-bit at 2.5v reference 12 lsb dac differential nonlinearity dacdnl 12-bit at 2.5v reference, guaranteed by design, not production tested 1 lsb dac offset v offset-dac at code 0 0 18 mv dac source load regulation i dac-source 0 to full-scale output 8.6 mv/ma dac sink capability and sink load regulation r dac-sink 0 to 0.5v output, limited by output buffer impedance 500 i i dac-sink 0.5v to full-scale output 11.5 mv/ma dac settling time t dac output load capacitance between 33pf and 270pf, from 10% to 90% 10 fs parameter symbol conditions min typ max units fast comparator resolution fc r 8 bits fast comparator internal reference accuracy fcrefacc -1.25 +1.25 % fast comparator operating current i fastcomp see the dc electrical characteristics fast comparator full scale v fs-comp 2.38 2.42 2.48 v fast comparator integral nonlinearity inl differential mode, 2.2nf capacitor at input, tested at worst-case positions 2 lsb fast comparator differential nonlinearity dnl differential mode, 2.2nf capacitor at input, guaranteed by design 1 lsb fast comparator offset v offset-comp 2 lsb fast comparator input resistance r in-comp (note 6) 15 mi fast comparator input capacitance c in-comp 4 pf fast comparator sample rate f comp 625 ksps ds4830 optical microcontroller maxim integrated
5 adc dc electrical characteristics (v dd = 2.97v to 3.63v, t a = -40nc to +85nc, unless otherwise noted. typical values are at v dd = 3.3v, t a = +25nc.) sample/hold dc electrical characteristics (v dd = 2.97v to 3.63v, t a = -40nc to +85nc, unless otherwise noted. typical values are at v dd = 3.3v, t a = +25nc.) parameter symbol conditions min typ max units adc resolution adc r default or slow adc clock setting 13 bits adc internal reference accuracy adcrefacc -0.85 +0.85 % adc operating current i adc see the dc electrical characteristics adc full-scale 1 v fs-adc1 1.2 v adc full-scale 2 v fs-adc2 0.6 v adc full-scale 3 v fs-adc3 2.4 v adc full-scale 4 v fs-adc4 4.8 v adc integral nonlinearity adcinl computed using end points best fit: 13-bit, +25c, v dd = 3.3v, v fs-adc3 10 lsb adc differential nonlinearity adcdnl v fs = 1.2v 0.5 lsb adc sample-sample deviation adc full-scale set to v fs-adc3 5 lsb adc offset v offset-adc 13-bit, v fs = 1.2v -8 +1 +8 lsb gp[15:0] input resistance r in-adc 15 mi adc sample rate f sample (note 7) 8 ksps adc temperature conversion time t temp 4.2 ms internal temperature measurement error tint err (note 8) 2 nc remote temperature measurement error (ds4830 error only) trem err (note 8) 2 nc parameter symbol conditions min typ max units sample/hold input range v shp adc-shn[1:0] = gnd 0 1 v sample/hold capacitance c sh adc-shp[1:0] to adc-shn[1:0] 5 pf sample input leakage i shlkg adc-shp[1:0] and adc-shn[1:0] connected to gnd 1.2 fa sample time t s adc-shp[1:0] and adc-shn[1:0] connected to 50i voltage source 300 ns sample conversion complete t h time from valid sample to adc data available 320 fs sample offset v sh-off measured at 10mv -10 -1.6 +7 mv sample error err sh v adc-shp_ to v adc-shn_ = 300mv, t s = 300ns, driven with 50i voltage source -4 +4 % sample discharge strength r dis adc-shp[1:0] or adc-shn[1:0] to gnd 900 i ds4830 optical microcontroller maxim integrated
6 flash memory dc electrical characteristics (v dd = 2.97v to 3.63v, t a = -40nc to +85nc, unless otherwise noted. typical values are at v dd = 3.3v, t a = +25nc.) i 2 c-compatible interface electrical characteristics (v dd = 2.97v to 3.63v, t a = -40nc to +85nc, unless otherwise noted.) (see figure 1.) parameter symbol conditions min typ max units flash erase time t me mass erase 22.9 24.14 25.35 ms t pe page erase 22.9 24.14 25.35 flash programming time per word t prog (note 9) 69 74 79 s flash programming temperature t flash -40 +85 nc flash endurance n flash t a = +50nc, guaranteed by design 20,000 write cycles data retention t ret t a = +50nc, guaranteed by design 100 years parameter symbol conditions min typ max units scl/mscl clock frequency f scl timeout not enabled 400 khz scl bootloader clock frequency f scl:boot 100 khz bus free time between a stop and start condition t buf 1.3 fs hold time (repeated) start condition t hd:sta (note 10) 0.6 fs low period of scl/mscl clock t low 1.3 fs high period of scl/mscl clock t high 0.6 fs setup time for a (repeated) start condition t su:sta 0.6 fs data hold time (note 11) t hd:dat receive 0 ns transmit 300 data setup time t su:dat (note 12) 100 ns scl/mscl, sda/msda capacitive loading c b (note 12) 400 pf rise time of both sda and scl signals t r (note 12) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 12) 20 + 0.1c b 300 ns setup time for stop condition t su:sto 0.6 fs spike pulse width that can be suppressed by input filter t sp (note 13) 50 ns scl/mscl and sda/msda input capacitance c bin 5 pf smbus timeout t smbus 30 ms ds4830 optical microcontroller maxim integrated
7 3-wire digital interface specification (v dd = 2.97v to 3.63v, t a = -40nc to +85nc, unless otherwise noted.) (see figure 2.) spi digital interface specification (v dd = 2.97v to 3.63v, t a = -40nc to +85nc, unless otherwise noted.) (see figure 3 and figure 4.) parameter symbol conditions min typ max units mcl clock frequency f sclout 1000 khz mcl duty cycle t 3wdc 50 % mdio setup time t ds 100 ns mdio hold time t dh 100 ns mcs pulse-width low t csw 500 ns mcs leading time before the first mcl edge t l 500 ns mcs trailing time after the last mcl edge t t 500 ns mdio, mcl load c b3w total bus capacitance on one line 10 pf parameter symbol conditions min typ max units spi master operating frequency 1/t mspick f sys /2 mhz spi slave operating frequency 1/t sspick f sys /4 mhz spi i/o rise/fall time t spi_rf c l = 15pf, pullup = 560i 25 ns mspick output pulse-width high/low t mch , t mcl t mspick /2 - t spi_rf ns mspido output hold after mspick sample edge t moh t mspick /2 - t spi_rf ns mspido output valid to mspick sample edge (mspido setup) t mov t mspick /2 - t spi_rf ns mspidi input valid to mspick sample edge (mspidi setup) t mis 2t spi_rf ns mspidi input to mspick sample edge rise/fall hold t mih 0 ns mspick inactive to mspido inactive t mlh t mspick /2 - t spi_rf ns sspick input pulse-width high/ low t sch , t scl t sspick /2 ns sspics active to first shift edge t sse t spi_rf ns sspidi input to sspick sample edge rise/fall setup t sis t spi_rf ns sspidi input from sspick sample edge transition hold t sih t spi_rf ns ds4830 optical microcontroller maxim integrated
8 spi digital interface specification (continued) (v dd = 2.97v to 3.63v, t a = -40nc to +85nc, unless otherwise noted.) (see figure 3 and figure 4.) electrical characteristics: jtag interface (v dd = 2.97v to 3.63v, t a = -40nc to +85nc, unless otherwise noted.) (figure 5) note 1: all voltages are referenced to gnd. currents entering the ic are specified as positive, and currents exiting the ic are specified as negative. note 2: maximum current assuming 100% cpu duty cycle. note 3: this value does not include current in gpio, scl, sda, mdio, mdi, mcl, refina, and refinb. note 4: using internal reference. note 5: there is one internal oscillator. the oscillator (peripheral clock) goes through a 2:1 divider to create the core clock. note 6: guaranteed by design. note 7: adc conversions are delayed up to 1.6fs if the fast comparator is sampling the selected adc channel. this can cause a slight decrease in the adc sampling rate. note 8: temperature readings average 64 times. note 9: programming time does not include overhead associated with the utility rom interface. note 10: f scl must meet the minimum clock low time plus the rise/fall times. note 11: this device internally provides a hold time of at least 75ns for the sda signal (referred to the v ih:min of the scl signal) to bridge the undefined region of the falling edge of scl. note 12: c b total capacitance of one bus line in pf. note 13: filters on sda and scl suppress noise spikes at the input buffers and delay the sampling instant. parameter symbol conditions min typ max units sspido output valid after sspick shift edge transition t sov 2t spi_rf ns sspics inactive t ssh t sspick + t spi_rf ns sspick inactive to sspics rising t sd t spi_rf ns sspido output disabled after sspics edge rise t slh 2t sspick + 2t spi_rf ns parameter symbol conditions min typ max units jtag logic reference v ref v dd /2 v tck high time t th 0.5 fs tck low time t tl 0.5 fs tck low to tdo output t tlq 0.125 fs tms, tdi input setup to tck high t dvth 0.25 fs tms, tdi input hold after tck high t thdx 0.25 fs ds4830 optical microcontroller maxim integrated
9 timing diagrams figure 1. i 2 c timing diagram figure 2. 3-wire timing diagram scl/ mscl note: timing is referenced to v ilmax and v ihmin . sda/ msda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low mcs mcl mdio mcs mcl mcs 12 3 456 78 a6 91 01 11 21 31 41 5 0 12 3 456 78 91 01 11 21 31 41 5 0 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 write mode read mode a0 a6 a5 a4 a3 a2 a1 a0 t l t l t ds t dh t ds t dh t t t t r/w r/w ds4830 optical microcontroller maxim integrated
10 timing diagrams (continued) figure 3. spi master communications timing diagram figure 4. spi slave communications timing diagram mspics (sas = 0) mspick ckpol/ckpha mspick ckpol/ckpha 1/0 0/1 1/1 0/0 1/0 0/1 1/1 0/0 mspido mspidi lsb lsb shift sample shift sample t mspick t mch t moh t mis t mov t spi_rf t mlh t mih t mcl msb msb-1 msb msb-1 shift sample shift sample sspics (sas = 1) sspidi sspido t sse t sspick t sch t scl t sis t sov t slh t ssh t sd t spi_rf t sih msb msb-1 msb msb-1 lsb lsb sspick ckpol/ckpha sspick ckpol/ckpha 1/0 0/1 1/1 0/0 1/0 0/1 1/1 0/0 ds4830 optical microcontroller maxim integrated
11 timing diagrams (continued) figure 5. jtag timing diagram tck tms/tdi tdo v ref t th t tlq t tl t thdx t dvth ds4830 optical microcontroller maxim integrated
12 typical operating characteristics (t a = +25c, unless otherwise noted.) dac inl (lsb) ds4830 toc01 setting (dec) dac inl (lsb) 4000 3500 2500 3000 1000 1500 2000 500 -4 -3 -2 -1 0 1 2 3 4 5 -5 0 dac dnl (lsb) ds4830 toc02 setting (dec) dac dnl (lsb) 4000 3500 2500 3000 1000 1500 2000 500 -0.9 -0.8 -0.6 -0.4 -0.2 0 0.2 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -1.0 0 adc inl (lsb) ds4830 toc03 input voltage (v) adc inl (lsb) 2.0 1.5 1.0 0.5 -8 -3 2 7 12 -13 0 adc dnl (lsb) ds4830 toc04 input voltage (v) adc dnl (lsb) 2.0 1.5 1.0 0.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 2.5 ds4830 optical microcontroller maxim integrated
13 pin configuration pin description pin name input structure(s) output structure power-on state selectable functions (first column is default function) port 1 rst digital open drain high impedance rst 2 scl digital open drain high impedance i 2 c slave clock scl spi sspick 3 sda digital open drain high impedance i 2 c slave data sda spi sspidi 4 gp0 adc/digital input push-pull, extra strong 55a pullup adc-s0 adc- d0p pw0 p2.0 5 reg285 v reg none 2.85v only function is for bypass capacitor for 2.85v internal regulator 6 gp1 adc/digital input push-pull, extra strong 55a pullup adc-s1 adc- d0n pw1 p2.1 7 v dd voltage supply, adc input none v dd adc-vdd 8 gp2 sh input, adc input none high impedance adc-s2 adc- shp0 adc- d1p tqfn (5mm x 5mm) top view 35 36 34 33 12 11 13 scl gp0 reg285 gp1 v dd 14 rst mcs mdi mdio v dd pw9 pw8 shen gp15 12 dacpw2 45 67 27 28 29 30 26 24 23 22 dacpw3 dacpw4 gp11 gp10 reg18 gp9 sda mcl 3 25 37 dacpw5 gp8 38 39 40 dacpw6 refinb dacpw7 gp7 gp6 gp5 ep + dacpw1 32 15 gp12 dacpw0 31 16 17 18 19 20 gp13 gp2 gp3 gp4 gp14 89 10 21 refina ds4830 ds4830 optical microcontroller maxim integrated
14 pin description (continued) pin name input structure(s) output structure power-on state selectable functions (first column is default function) port 9 gp3 sh input, adc input none high impedance adc-s3 adc- shn0 adc- d1n 10 gp4 adc/digital input push-pull 55a pullup jtag tck adc-s4 adc- d2p p6.0 11 gp5 adc/digital input push-pull 55a pullup jtag tdi adc-s5 adc- d2n p6.1 12 gp6 adc/digital input push-pull 55a pullup adc-s6 adc- d3p pw2 spi sspido p2.2 13 gp7 adc/digital input push-pull 55a pullup adc-s7 adc- d3n pw3 spi sspics p2.3 14 gp8 adc/digital i/p, external temp a+ i/p (adc-text_a) push-pull 55a pullup adc-s8 adc- d4p p2.4 15 gp9 adc/digital i/p, external temp a- i/p (adc-text_a) push-pull 55a pullup adc-s9 adc- d4n p2.5 16 reg18 v reg none 1.8v pin for 1.8v regulator bypass capacitor 17 gp10 adc/digital i/p, external temp a+ i/p (adc-text_b) push-pull 55a pullup jtag tms adc- s10 adc- d5p p6.2 18 gp11 adc/digital i/p, external temp a+ i/p (adc-text_b) push-pull 55a pullup jtag tdo adc- s11 adc- d5n p6.3 19 gp12 sh input, adc/digital input push-pull 55a pullup adc-s12 adc- shp1 adc- d6p p0.0 20 gp13 sh input, adc/digital input push-pull 55a pullup adc-s13 adc- shn1 adc- d6n p0.1 21 gp14 adc/digital input push-pull 55a pullup adc-s14 adc- d7p shen1 p0.2 22 gp15 adc/digital input push-pull 55a pullup adc-s15 adc- d7n p0.3 23 shen digital push-pull 55a pullup shen0 p6.4 24 mdio digital push-pull 55a pullup 3-wire data mdio i 2 c msda spi mspido pw4 p1.0 25 mdi digital push-pull, strong 55a pullup spi mspidi pw5 p1.3 26 mcl digital push-pull 55a pullup 3-wire clock mcl i 2 c mscl spi mspick pw6 p1.1 ds4830 optical microcontroller maxim integrated
15 pin description (continued) pin name input structure(s) output structure power-on state selectable functions (first column is default function) port 27 mcs digital push-pull, extra strong 55a pullup 3-wire chip select mcs spi mspics pw7 p1.2 28 v dd voltage supply none v dd adc-vdd 29 pw9 digital push-pull, extra strong 55a pullup pw9 p0.7 30 pw8 digital push-pull, extra strong 55a pullup pw8 p0.6 31 refina reference, adc/digital input (adc_refa) push-pull 55a pullup adc- refina p2.6 32 dacpw0 digital push-pull 55a pullup dac0, fs = refina or internal reference pw0 p0.4 33 dacpw1 digital push-pull 55a pullup dac1, fs = refina or internal reference pw1 p0.5 34 dacpw2 digital push-pull 55a pullup dac2, fs = refina or internal reference pw2 clkin p6.5 35 dacpw3 digital push-pull, strong 55a pullup dac3, fs = refina or internal reference pw3 p1.5 36 dacpw4 digital push-pull 55a pullup dac4, fs = refinb or internal reference pw4 p1.6 37 dacpw5 digital push-pull 55a pullup dac5, fs = refinb or internal reference pw5 p1.7 38 dacpw6 digital push-pull, strong 55a pullup dac6, fs = refinb or internal reference pw6 p6.6 39 refinb reference, adc/ digital input push-pull 55a pullup adc- refinb p1.4 ds4830 optical microcontroller maxim integrated
16 pin description (continued) note: bypass v dd , reg285, and reg18 each with a 1f x5r and 10nf capacitors to ground. all input-only pins and open-drain outputs are high impedance after v dd exceeds v bo and prior to code execution. pins configured as gpio have a weak internal pullup. see the selectable functions table for more information. selectable functions pin name input structure(s) output structure power-on state selectable functions (first column is default function) port 40 dacpw7 digital push-pull 55a pullup dac7, fs = refinb or internal reference pw7 p2.7 ep exposed pad (connect to gnd) gnd function name description adc-d[7:0][p/n] differential inputs to adc. also used for external temperature sensors. adc-refin[a/b] refina and refinb monitor inputs to adc adc-s[15:0] single-ended inputs to adc adc-sh[p/n][1:0] sample/hold inputs 1 and 0 adc-vdd v dd monitor input to adc dac[7:0] voltage dac outputs mcl, mcs, mdio maxim proprietary 3-wire interface, mcl (clock), mcs (chip select), mdio (data). used to control the max3798 family of high-speed laser drivers. mscl, msda i 2 c master interface: mscl (i 2 c master slave), msda (i 2 c master data) mspick, mspics, mspidi, mspido spi master interface: mspick (clock), mspics (active-low chip select), mspidi (data in), mspido (data out) p0.n, p1.n, p2.n, p6.n general-purpose inputs/outputs. can also function as interrupts. pw[9:0] pwm outputs rst used by jtag and as active-low reset for device scl, sda i 2 c slave interface: scl (i 2 c slave clock), sda (i 2 c slave data). these also function as a password-protected programming interface. shen[1:0] sample/hold enable inputs. can also function as interrupts. sspick, sspics, sspidi, sspido spi slave interface: sspick (clock), sspics (active-low chip select), sspidi (data in), sspido (data out). in spi slave mode, the i 2 c slave interface is disabled. tck, tdi, tdo, tms jtag interface pins. also includes rst. ds4830 optical microcontroller maxim integrated
17 block diagram clock control, watchdog timer, and power monitor ckcn wdcn ic ic ip loop counters data pointers dpc 4k x 16 utility rom ffffh 8fffh 8000h 7fffh 0000h program memory space lc[n] ap apc psf 10mhz cpu clock imr iir interrupt logic address generation dp[0], dp[1], fp = (bp+offs) 32k x 16 user program memory accumulators (16) boolean variable manipulation instruction decode (src, dst transport determination) 4k x 16 utility rom ffffh 8fffh 8000h 03ffh 0000h data memory space 1k x 16 sram sp stack memory 16 x 16 master: i 2 c spi 3-wire mdi mdio mcl mcs slave: i 2 c spi scl sda sspido sspics shen[1:0] gp[15:0] clkin refin[a/b] pw[9:0] dacpw[7:0] 16-bit timers x 2 20mhz osc /2 core clock memory management unit (mmu) rst 13-bit adc 8-bit comp d-pwm x 10 v dd adc-d[7:0][p/n] pwm[9:0] adc-s[15:0] internal temp refin[a/b] dac[7:0] 12-bit dac x 8 v ref up to 31 port pins gpio ds4830 c s x2 disch adc-shp[1:0] adc-shn[1:0] sample/hold ds4830 optical microcontroller maxim integrated
18 detailed description the following is an introduction to the primary features of the ds4830 optical microcontroller. more detailed descriptions of the device features can be found in the ds4830 users guide. microcontroller core architecture the device employs a low-power, low-cost, high-perfor- mance, 16-bit risc microcontroller with on-chip flash memory. it is structured on an advanced, 16 accumula- tor-based, 16-bit risc architecture. fetch and execution operations are completed in one cycle without pipelining, since the instruction contains both the op code and data. the highly efficient core is supported by 16 accumulators and a 16-level hardware stack, enabling fast subroutine calling and task switching. data can be quickly and efficiently manipulated with three internal data pointers. multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. the data pointers can auto- matically increment or decrement following an operation, eliminating the need for software intervention. module information top-level instruction decoding is extremely simple and based on transfers to and from registers. the registers are organized into functional modules, which are in turn divided into the system register and peripheral register groups. peripherals and other features are accessed through peripheral registers. these registers reside in modules 0 to 5. the following provides information about the spe- cific module in which each peripheral resides: ? module 0: timer 1, gpio ports 0, 1, and 2 ? module 1: i 2 c master, gpio port 6, spi slave, svm ? module 2: i 2 c slave, analog-to-digital converter (adc), sample/hold, temperature, 3-wire master ? module 3: timer 2, mac-related registers ? module 4: digital-to-analog converter (dac) ? module 5: quick trips, spi master, pwm instruction set the instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory loca- tions. the instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. special-function registers control the peripherals and are subdivided into register modules. memory organization the device incorporates several memory areas: ? 32 kwords of flash memory for application program storage ? 1 kwords of sram for storage of temporary variables ? 4 kwords of utility rom contain a debugger and pro- gram loader ? 16-level stack memory for storage of program return addresses and general-purpose use the memory is implemented with separate address spaces for program memory, data memory, and register space. rom, application code, and data memory can be placed into a single contiguous memory map. the device allows data memory to be mapped into program space, permitting code execution from data memory. in addition, program memory can be mapped into data space, per- mitting code constants to be accessed as data memory. figure 6 shows the ds4830s memory map when execut- ing from program memory space. refer to the ds4830 users guide for memory map information when execut- ing from data or rom space. the incorporation of flash memory allows field upgrade of the firmware. flash memory can be password protected with a 16-word key, denying access to program memory by unauthorized individuals. utility rom the utility rom is a 4 kword block of internal rom memory that defaults to a starting address of 8000h. the utility rom consists of subroutines that can be called from application software, which includes the following: ? in-system programming (bootstrap loader) over jtag or i 2 c-compatible interfaces ? in-circuit debug routines ds4830 optical microcontroller maxim integrated
19 figure 6. memory map when program is executing from flash memory ? internal self-test routines ? callable routines for in-application flash programming following any reset, execution begins in the utility rom. the rom software determines whether the program execution should immediately jump to location 0000h, the start of application code, or to one of the special routines mentioned. routines within the utility rom are firmware-accessible and can be called as subroutines by the application software. more information on the utility rom contents is contained in the ds4830 users guide. password some applications require protection against unau- thorized viewing of program code memory. for these applications, access to in-system programming, in-appli- cation programming, or in-circuit debugging functions is prohibited until a password has been supplied. the password is defined as the 16 words of physical program memory at addresses 0010hC001fh. a single password lock (pwl) bit is implemented in the device. when the pwl is set to 1 (power-on-reset default) and the contents of the memory at addresses 0010hC001fh are any value other than all ffh or 00h, the password is required to access the utility rom, includ- ing in-circuit debug and in-system programming routines that allow reading or writing of internal memory. when pwl is cleared to 0, these utilities are fully accessible without the password. the password is automatically set to all ones following a mass erase. detailed information regarding the password can be found in the ds4830 users guide. system registers peripheral registers dp 16 x 16 stack m5 m4 m3 m2 m1 m0 5h 0fh 00h 4h 3h 2h 1h 0h ffffh ffffh ffffh 8fffh 9fffh 8fffh 7fffh 0000h 0000h 0000h 4k x 16 utility rom 8k x 8 utility rom 4k x 16 utility rom 2k x 8 sram data 1k x 16 sram data 32k x 16 user program memory 8000h 8000h 8000h 07ffh 03ffh dpc sp ip pfx a ap fh 00h 0fh 00h 1fh eh dh ch bh 9h 8h program memory space data memory (byte mode) data memory (word mode) 001fh 0010h password ds4830 optical microcontroller maxim integrated
20 stack memory a 16-bit, 16-level internal stack provides storage for pro- gram return addresses. the stack is used automatically by the processor when the call, ret, and reti instruc- tions are executed and interrupts serviced. the stack can also be used explicitly to store and retrieve data by using the push, pop, and popi instructions. on reset, the stack pointer, sp, initializes to the top of the stack (0fh). the call, push, and interrupt-vectoring operations increment sp, then store a value at the location pointed to by sp. the ret, reti, pop, and popi opera- tions retrieve the value at sp and then decrement sp. programming the microcontrollers flash memory can be programmed by one of two methods: in-system programming or in- application programming. these provide great flexibility in system design as well as reduce the life-cycle cost of the embedded system. programming can be password pro- tected to prevent unauthorized access to code memory. in-system programming an internal bootstrap loader allows the device to be pro- grammed over the jtag or i 2 c compatible interfaces. as a result, system software can be upgraded in-system, eliminating the need for a costly hardware retrofit when software updates are required. the programming source select (pss) bits in the icdf register determine which interface is used for bootload- ing operation. the device supports jtag and i 2 c as an interface corresponding to the 00 and 01 bits of pss, respectively. see figure 7. in-application programming the in-application programming feature allows the micro- controller to modify its own flash program memory. this allows on-the-fly software updates in mission-critical applications that cannot afford downtime. alternatively, it figure 7. in-system programming ds4830 reset initiated by por, i 2 c self-reset, or rst pin. reset device. begin boot rom code execution at 8000h. wait for 320 system cycles (32s). reset i 2 c. set pwl bit. set rod bit. bootloader set pss[1:0] = 01 rom code enables slave i 2 c interface: address is 36h. is jtag_spe bit set? no yes set using jtag programmer, followed by reset of device. waits for exit loader command from hos t set by writing f0h to i 2 c slave 34h. jump to user code (flash) at 0000h. is i2c_spe bit set? no yes ds4830 optical microcontroller maxim integrated
21 allows the application to develop custom loader software that can operate under the control of the application soft- ware. the utility rom contains firmware-accessible flash programming functions that erase and program flash memory. these functions are described in detail in the ds4830 users guide. register set sets of registers control most device functions. these registers provide a working space for memory opera- tions as well as configuring and addressing peripheral registers on the device. registers are divided into two major types: system registers (special-purpose registers, or sprs) and peripheral registers (special-function reg- isters, or sfrs). the common register set, also known as the system registers, includes the alu, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. the peripheral registers define addi- tional functionality, and the functionality is broken up into discrete modules. both the system registers and the peripheral registers are described in detail in the ds4830 users guide. system timing the device generates its 10mhz instruction clock (mosc) internally. on power-up, the oscillators output (which cannot be accessed externally) is disabled until v dd rises above v bo . once this threshold is reached, the output is enabled after approximately 1ms, clocking the device. see figure 8. system reset the device features several sources that can be used to reset the ds4830. power-on reset an internal power-on-reset (por) circuit is used to enhance system reliability. this circuit forces the device to perform a por whenever a rising voltage on v dd climbs above v bo . when this happens the following events occur: ? all registers and circuits enter their reset state. ? the por flag (wdcn.7) is set to indicate the source of the reset. ? code execution begins at location 8000h when the reset condition is released. brownout detect/reset the device features a brownout detect/reset function. whenever the power monitor detects a brownout condi- tion (when v dd < v bo ), it immediately issues a reset and stays in that state as long as v dd remains below v bo . once v dd voltage rises above v bo , the device waits for t su:mosc before returning to normal operation, also referred to as cpu state. if a brownout occurs during t su:mosc , the device again goes back to the brownout state. otherwise, it enters into cpu state. in cpu state, the brownout detector is also enabled. on power-up, the device always enters brownout state first and then follows the above sequence. the reset issued by brownout is the same as por. any action performed after por also happens on brownout reset. figure 8. system timing t su:mosc = ~1ms core clock v dd v bo ds4830 optical microcontroller maxim integrated
22 all the registers that are cleared on por are also cleared on brownout reset. watchdog timer reset the watchdog timer provides a mechanism to reset the processor in the case of undesirable code execution. the watchdog timer is a hardware timer designed to be peri- odically reset by the application software. if the software operates correctly, the timer is reset before it reaches its maximum count. however, if undesirable code execution prevents a reset of the watchdog timer, the timer reaches its maximum count and resets the processor. the watchdog timer is controlled through two bits in the wdcn register (wdcn[5:4]: wd[1:0]). its timeout period can be set to one of the four programmable intervals ranging from 2 12 to 2 21 system clock (mosc) periods (0.409ms to 0.210s). the watchdog interrupt occurs at the end of this timeout period, which is 512 mosc clock periods, or approximately 50fs, before the reset. the reset generated by the watchdog timer lasts for four sys - tem clock cycles, which is 0.4fs. software can determine if a reset is caused by a watchdog timeout by checking the watchdog timer reset flag (wtrf) in the wdcn reg- ister. execution resumes at location 8000h following a watchdog timer reset. external reset asserting rst low causes the device to enter the reset state. the external reset function is described in the ds4830 users guide. execution resumes at location 8000h after rst is released. the dac and pwm outputs are unchanged during execution of external reset. internal system reset the host can issue an i 2 c command (bbh) to reset the communicating device. this reset has the same effect as the external reset as far as the reset values of all registers are concerned. also, an internal system reset can occur when the in-system programming is done (rod = 1). the dac and pwm outputs are unchanged during execution of an internal reset. further details are available in the ds4830 users guide. programmable timer the device features two general-purpose programmable timers. various timing loops can be implemented using the timers. each general-purpose timer uses three sfrs. gtcn is the general control register, gtv is the timer value regis- ter, and gtc is the timer compare register. the timer can be used in two modes: free-running mode and compare mode with interrupts. both are described in detail in the ds4830 users guide. the functionality of the timers can be accessed through three sfrs for each of the general-purpose timers. the timer sfrs are accessed in module 0 and module 3. detailed information regarding the timer block can be found in the ds4830 users guide. hardware multiplier the hardware multiplier (multiply-accumulate, or mac module) is a very powerful tool, especially for applica- tions that require heavy calculations. this multiplier can execute the multiply or multiply-negate, or multiply- accumulate or multiply-subtract operation for signed or unsigned operands. the mac module uses eight sfrs, mapped as register 0hC05h and 08hC09h in module m3. system interrupts multiple interrupt sources are available to respond to internal and external events. the microcontroller archi- tecture uses a single interrupt vector (iv) and single interrupt-service routine (isr) design. for maximum flex- ibility, interrupts can be enabled globally, individually, or by module. when an interrupt condition occurs, its indi- vidual flag is set, even if the interrupt source is disabled at the local, module, or global level. interrupt flags must be cleared within the firmware-interrupt routine to avoid repeated interrupts from the same source. application software must ensure a delay between the write to the flag and the reti instruction to allow time for the inter- rupt hardware to remove the internal interrupt condition. asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a two- instruction delay. when an enabled interrupt is detected, execution jumps to a user-programmable interrupt vector location. the iv register defaults to 0000h on reset or power-up, so if it is not changed to a different address, application firmware must determine whether a jump to 0000h came from a rst or interrupt source. once control has been transferred to the isr, the inter - rupt identification register (iir) can be used to determine if a system register or peripheral register was the source of the interrupt. in addition to iir, miir registers are implemented to indicate which particular function under a peripheral module has caused the interrupt. the device ds4830 optical microcontroller maxim integrated
23 contains six peripheral modules, m0 to m5. an miir reg- ister is implemented in modules m1 and m2. the miirs are 16-bit read-only registers and all of them default to all zeros on system reset. once the module that causes the interrupt is singled out, it can then be interrogated for the specific interrupt source and software can take appropriate action. interrupts are evaluated by applica- tion code allowing the definition of a unique interrupt priority scheme for each application. interrupt sources are available from the watchdog timer, the adc (includ- ing sample/holds), fast comparators, the programmable timer, svm, the i 2 c-compatible master and slave inter- face, 3-wire, master and slave spi, and all gpio pins. i/o port the device allows for most inputs and outputs to function as general-purpose input and/or output pins. there are four ports: p0, p1, p2, and p6. note that there is no port corresponding to p6.7. the 7th bit of port 6 is nonfunc- tional in all sfrs. each pin is multiplexed with at least one special function, such as interrupts, i/o pins, or jtag pins, etc. the gpio pins have schmitt trigger receivers and full cmos output drivers and can support alternate functions. the ports can be accessed through sfrs (po[0,1,2,6], pi[0,1,2,6], pd[0,1,2,6], eie[0,1,2,6], eif[0,1,2,6], and eies[0,1,2,6]) in modules 0 and 1, and each pin can be individually configured. the pin is either high impedance or a weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. in addition, each pin can function as external interrupt with individual enable, flag and active edge selection, when programmed as input. the i/o port sfrs are accessed in module 0 and 1. detailed information regarding the gpio block can be found in the ds4830 users guide. dac outputs the device provides eight 12-bit dac outputs with multi- ple reference options. an internal 2.5v reference is pro- vided. there are also two selectable external references. refina can be selected as the full-scale reference for dac0 to dac3. refinb can be selected as the full-scale reference for dac4 to dac7. the dac outputs are volt- age buffered. each dac can be individually disabled and put into a low-power power-down mode using daccfg. an external reset does not affect the dac outputs. if a dac output is used during the lifetime of the ds4830, the dac must always be enabled to guarantee meeting the inl and offset specifications. if a pin is used for a dac, it should be used only for the dac function. the pins function should not be switched between dac and pwm or switched between dac and gpio. the dac sfrs are accessed in module 4. detailed information regarding the dac block can be found in the ds4830 users guide. pwm outputs the device provides 10 independently configurable pwm outputs. the pwm outputs are configured using three sfrs: pwmcn, pwmdata, and pwnsync. using pwmcn and pwmdata, individual pwm channels can be programmed for unique duty cycles (dcycn), con- figurations (pwmcfgn), and delays (pwmdlyn), where n represents the pwm channel number. the pwm clock can be obtained from the core clock, peripheral clock, or an external clock, depending on clk_sel bits programmed in individual pwmcfgn reg- isters. the pwmcfgn register also enables/disables the corresponding pwm output and selects the pwm polar - ity. the user can set the duty cycle and the frequency of each pwm output individually by configuring the cor - responding dcycn register and the pwmcfgn register. the device allows 4-slot or 32-slot pulse spreading options for each pwm channel. the pwm outputs can be configured to be output on an alternate location using the configuration register. pwmdly is a 12-bit register used for providing starting delay on different pwm channels, and can be used to create multiphase pwm operation. different channels can be synchronized using the pwmsync register. doing so effectively brings the channels in phase by restarting the channels that are to be synchronized. an external reset does not affect the pwm outputs. the pwm sfrs are accessed in module 5. detailed information regarding the pwm block can be found in the ds4830 users guide. ds4830 optical microcontroller maxim integrated
24 analog-to-digital converter and sample/hold the analog-to-digital converter (adc) controller is the digital interface block between the cpu and the adc. it provides all the necessary controls to the adc and the cpu interface. the adc uses a set of sfrs for configur- ing the adc in desired mode of operation. the device contains a 13-bit adc with an input mux ( figure 9 ). the mux selects the adc input from 16 single- ended or eight differential inputs. additionally, the chan- nels can be configured to convert internal and external temperature, v dd , internal reference, or refina/b. two channels can be programmed to be sample/hold inputs. the internal channel is used exclusively to measure the die temperature. the sfr registers control the adc. adc when used in voltage input mode, the voltage applied on the corresponding channel (differential or single-ended) is converted to a digital readout. the adc can be set up to continuously poll selected input channels (continuous- sequence mode) or run a short burst of conversions and enter a shutdown mode to conserve power (single- sequence mode). in voltage mode there are four full-scale values that can be programmed. these values can be trimmed by modi- fying the associated gain registers (adcg1, adcg2, adcg3, adcg4). by default these are set to 1.2v, 0.6v, 2.4v, and 4.8v full scale. the adcclk is derived from the system clock with divi- sion ratio defined by the adc control register. an a/d conversion takes 15 adcclk cycles to complete with additional four core clocks used for data processing. internally every channel is converted twice and the aver - age of two conversions is written to the data buffer. this gives each conversion result in (30 x adc clock period + 800ns). adc sampling rate is approximately 40ksps for the fastest adc clock (core clock/8). in applications where extending the acquisition time is desired, the sam- ple can be acquired over a prolonged period determined by the adc control register. each adc channel can have its own configuration, such as differential mode select, data alignment select, acqui- sition extension enable, and adc gain select, etc. the adc also has 24 (0 to 23) 16-bit data buffers for con- version result storage. the adc data available interrupt flag (addai) can be configured to trigger an interrupt following a predetermined number of samples. once set, addai can be cleared by software or at the start of a conversion process. sample/hold pin combinations gp2-gp3 and gp12-gp13 can be used for sample/hold conversions if enabled in the shcn register. these two can be independently enabled or disabled by writing a 1 or 0 to their corresponding bit locations in shcn register. a data buffer location is reserved for each channel. when a particular channel is enabled, a sample of the input voltage is taken when a signal is issued on the shen pin, converted and stored in the corresponding data buffer. the two sample/hold channels can sample simultane- ously on the same shen signal or different shen signals depending on the sh_dual bit in the shcn sfr. the sample/hold data available interrupt flag (shndai) can be configured to trigger an interrupt following sam - ple completion. once set, shndai can be cleared by software. each sample/hold circuit consists of a sampling capaci - tor, charge injection nulling switches, and a buffer. also included is a discharge circuit used to discharge parasitic capacitance on the input node and the sample capacitor before sampling begins. the negative input pins can be used to reduce ground offsets and noise. figure 9. adc block diagram adc-s[15:0] adc-d[7:0][p/n] adc-shp[1:0] adc-shn[1:0] adc-refin[a/b] adc-vdd adc-vref_2.5v adc-text_a(+/-) adc-text_b(+/-) adc-tint mux adconv (start conversation) adccfg pga adgain 13-bit adc ds4830 optical microcontroller maxim integrated
25 temperature measurement the device provides an internal temperature sensor for die temperature monitoring and two external remote temperature-sensing channels. in external temperature mode, current is forced into an external diode that is con- nected between user-specified channel pins (gp8-gp9 or gp10-gp11). the diode temperature is obtained by measuring the diode voltages at multiple bias currents. these temperature channels can be enabled independ- ently by setting the appropriate bit locations in the tempcn register. whenever a temperature conversion is complete, the corresponding flag (intdai for internal conversion, ex0dai and ex1dai for external conversion) is set. these can be configured to cause an interrupt, and can be cleared by software. the temperature meas- urement resolution is 0.0625nc. the device can use all the three modes explained above simultaneously by using a time-slicing mechanism per - formed by the internal controller. the adc-related sfrs are accessed in module 1 and module 2. for details about this and the three blocks, refer to the adc section of the ds4830 users guide. fast comparator/quick trips the device supports 8-bit quick-trip comparison function- ality. the quick trips are required to continuously monitor user-defined channels in a round-robin sequence. the quick- trip controller allows the user control of the list of channels to monitor. each mode has a corresponding choice of list of channels for the round robin. in any mode of quick-trip operation, the quick trip (ana- log) performs two comparisons on any selected channel. 1) comparison with a high-threshold value. 2) comparison with a low-threshold value. any comparison above the high-threshold value or below the low-threshold value causes a bit to set in the cor- responding register. this bit can be used to trigger an interrupt. the threshold values are stored in 32 internal register (16 for low-threshold settings and 16 for high- threshold settings). the quick-trip controller provides the appropriate sequence of clock and threshold values for the quick trips. because the quick trips and the adc use the same input pins, the controller ensures that no colli- sion takes place. the quick-trip-related sfrs are accessed in module 5. refer to the quick trip section of the ds4830 users guide for more information. i 2 c-compatible interface modules the device provides two independent i 2 c-compatible interfaces: one is a master and the other is a slave. i 2 c-compatible master interface the device features an internal i 2 c-compatible master interface for communication with a wide variety of exter - nal i 2 c devices. the i 2 c-compatible master bus is a bidirectional bus using two bus lines: the serial-data line (msda) and the serial-clock line (mscl). for the i 2 c- compatible master, the device has ownership of the i 2 c bus and drives the clock and generates the start and stop signals. this allows the device to send data to a slave or receive data from a slave. when the i 2 c-compatible master interface is disabled, msda and mscl can be used as gpio pins p1.0 and p1.1, respectively, and accessed through po1/pi1/pd1. i 2 c-compatible slave interface the device also features an internal i 2 c-compatible slave interface for communication with a host. furthermore, the device can be in-system programmed (bootloaded) through the i 2 c-compatible slave interface. the two inter- face signals used by the i 2 c slave interface are scl and sda. for the i 2 c-compatible slave interface, the device relies on an externally generated clock to drive scl and responds to data and commands only when requested by the i 2 c master device. the i 2 c-compatible slave inter- face is open drain and requires external pullup resistors. smbus timeout both the i 2 c-compatible master and slave interfaces can work in smbusk-compatible mode for communication with other smbus devices. to achieve this, a 30ms timer has been implemented on the i 2 c-compatible slave inter - face to make the interface smbus compatible. the pur- pose of this timer is to issue a timeout interrupt and thus the firmware can reset the i 2 c-compatible slave interface when the scl is held low for longer than 30ms. the timer only starts when none of the following conditions is true: 1) the i 2 c-compatible slave interface is in the idle state and there is no communications on the bus. 2) the i 2 c-compatible slave interface is not working in smbus-compatible mode. smbus is a trademark of intel corp. ds4830 optical microcontroller maxim integrated
26 3) the scl logic level is high. 4) the i 2 c-compatible slave interface is disabled. when a timeout occurs, the timeout bit is set and an inter- rupt is generated, if enabled. the i 2 c master-related sfrs are accessed in module 1. the i 2 c slave-related sfrs are accessed in module 2. details can be found in the i 2 c section of the ds4830 users guide. serial peripheral interface module the device supports master and slave spi interfaces. the spi provides an independent serial communication channel to communicate synchronously with peripheral devices in a multiple master or multiple slave system. the interface allows access to a four-wire, full-duplex serial bus, and can be operated in either master mode or slave mode. collision detection is provided when two or more masters attempt a data transfer at the same time. the maximum data rate of the spi is 1/4 the system reference clock frequency for slave mode and 1/2 the system clock frequency for master mode. the four interface signals used by the spi are as follows: ? master in-slave out. this signal is an output from a slave device, sspido, and an input to the master device, mspidi. it is used to serially transfer data from the slave to the master. data is transferred most significant bit (msb) first. the slave device places this pin in an input state with a weak pullup when it is not selected. ? master out-slave in. this signal is an output from a master device, mspido, and an input to the slave devices, sspidi. it is used to serially transfer data from the master to the slave. data is transferred msb first. ? spi clock. this serial clock is an output from the mas- ter device, mspick, and an input to the slave devices, sspick. it is used to synchronize the transfer of data between the master and the slave on the data bus. ? active-low slave select. the slave-select signal is an input to enable the spi module in slave mode, sspics, by a master device. the spi module sup- ports configuration of an active sspics state through the slave-active select. normally, this signal has no function in master mode and its port pin can be used as a general-purpose i/o. however, the ssel can optionally be used as a mode fault detection in master mode. spi master interface the master mode is used when the devices spi controls the data transmission rates and data format. the spi is placed in master mode by setting the master mode bit (mstm). only an spi master device can initiate a data transfer. writing a data character to the spi data buffer (spib), when in master mode, starts a data transfer. the spi master immediately shifts out the data serially on mspido, msb first, while providing the serial clock on the mspick output. new data is simultaneously gated in on mspidi into the least significant bit (lsb) of the shift register. at the end of a transfer, the received data is loaded into the data buffer for reading, and the spi trans- fer complete flag (spic) is set. if spic is set, an interrupt request is generated to the interrupt handler, if enabled. spi slave interface slave mode is used when the spi is controlled by another peripheral device. the spi is in slave mode when an internal bit (mstm) is cleared to logic 0. in slave mode the spi is dependent on the sspick sourced from the master to control the data transfer. the sspick input frequency should not be greater than the system clock frequency of the slave device divided by 4. the spi mas- ter transfers data to a slave on sspidi, msb first, and the selected slave device simultaneously transfers the contents of its shift register to the master on sspido, also msb first. data received from the master replaces data in the slaves shift register at the completion of a transfer. just like in the master mode, received data is loaded into the read buffer, and the spi transfer complete flag is set at the end of the transfer. the setting of the transfer com- plete flag can cause an interrupt if enabled. the spi master-related sfrs are accessed in module 5. the spi slave-related sfrs are accessed in module 1. details can be found in the spi section of the ds4830 users guide. 3-wire interface module the ds4830 controls devices like the max3798/max3799 over a proprietary 3-wire interface. the ds4830 acts as the 3-wire master, initiating communication with and generating the clock for the max3798/max3799. it is a 3-pin interface consisting of mdio (a bidirectional data line), an mcl clock signal, and a mcs chip-select output (active high). the 3-wire master-related sfrs are accessed in mod- ule 2. detailed information regarding the 3-wire interface block can be found in the ds4830 users guide. ds4830 optical microcontroller maxim integrated
27 in-circuit debug embedded debugging capability is available through the jtag-compatible test access port (tap). embedded debug hardware and embedded rom firmware provide in-circuit debugging capability to the user application, eliminating the need for an expensive in-circuit emulator. figure 10 shows a block diagram of the in-circuit debug- ger. the in-circuit debug features include the following: ? a hardware debug engine ? a set of registers able to set breakpoints on register, code, or data accesses (icda, icdb, icdc, icdd, icdf, icdt0, and icdt1) ? a set of debug service routines stored in the utility rom the embedded hardware debug engine is an independ- ent hardware block in the microcontroller. the debug engine can monitor internal activities and interact with selected internal registers while the cpu is executing user code. collectively, the hardware and software fea- tures allow two basic modes of in-circuit debugging: ? background mode allows the host to configure and set up the in-circuit debugger while the cpu contin- ues to execute the application software at full speed. debug mode can be invoked from background mode. ? debug mode allows the debug engine to take control of the cpu, providing read/write access to internal reg- isters and memory, and single-step trace operation. applications information power-supply decoupling to achieve the best results when using the ds4830, decouple the v dd power supply with a 0.1 f f capaci- tor. use a high-quality, ceramic, surface-mount capaci- tor if possible. surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-fre- quency response for decoupling applications.decouple the reg285 and reg18 pins using 1ff x5r and 10nf capacitors (one each/per output). note: do not use either of these pins for external circuitry. additional documentation designers must have three documents to fully use all the features of this device. this data sheet contains pin descrip- tions, feature overviews, and electrical specifications. errata sheets contain deviations from published specifications. user guides offer detailed information about device features and operation. the following documents can be download - ed from www.maximintegrated.com/ds4830. ? this ds4830 data sheet, which contains electrical/timing specifications, package information, and pin descrip- tions. ? the ds4830 revision-specific errata sheet, if applicable. ? the ds4830 users guide, which contains detailed infor- mation and programming guidelines for core features and peripherals. development and technical support maxim and third-party suppliers provide a variety of highly versatile, affordably priced development tools for this microcontroller, including the following: ? compilers (c and assembly) ? in-circuit debugger ? integrated development environments (ides) ? serial-to-jtag converters for programming and debugging ? usb-to-jtag converters for programming and debugging a partial list of development tool vendors can be found at www.maximintegrated.com/maxq_tools. email mixedsignal.apps@maximintegrated.com for technical support. figure 10. in-circuit debugger tap controller cpu debug engine debug service routines (utility rom) control breakpoint address data ds4830 tms tck tdi tdo ds4830 optical microcontroller maxim integrated
28 ordering information +denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. *ep = exposed pad. package information for the latest package outline information and land patterns (foot- prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp range pin-package ds4830t+t -40nc to +85nc 40 tqfn-ep* package type package code outline no. land pattern no. 40 tqfn-ep t4055+2 21-0140 90-0002 ds4830 optical microcontroller maxim integrated
29 typical application circuit vcct vsel r1 touta 25i 25i toutc vout sda scl csel sda scl csel 13-bit adc slave i 2 c bias monitor md dfb max3948 ds4830 mode_def1 (scl) mode_def2 (sda) vcct vsel r2 touta 25i 25i toutc vout sda scl csel md dfb max3948 vcct vsel r3 touta 25i 25i toutc vout sda scl csel md dfb max3948 vcct vsel touta 25i 25i toutc vout sda scl csel md dfb max3948 v cc (+3.3v) rssi monitor ds4830 optical microcontroller maxim integrated
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 30 ? 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 6/11 initial release 1 10/11 corrected the lead temperature from +260nc to +300nc in the absolute maximum ratings section; added explanation to the dac outputs section about the dac operation to achieve desired inl levels 2, 22 2 6/13 style edits, rephrasing, edits to all electrical characteristics tables, values updated, typical operating characteristics added, block diagram updated, and updated figures 6, 7, 8 1C8, 12, 13, 15C27 ds4830 optical microcontroller

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